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Espressif Systems /ESP32-H2 /SPI1 /SPI_MEM_RD_STATUS

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Interpret as SPI_MEM_RD_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SPI_MEM_STATUS0SPI_MEM_WB_MODE

Description

SPI1 status register.

Fields

SPI_MEM_STATUS

The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
SPI_MEM_WB_MODE

Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data